PIC18F4610T-I/ML【PDF 65/234 页】IC MCU FLASH 32KX16 44QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3878

61页 62页 63页 64页 [65页]66页 67页 68页 69页

2009 Microchip Technology Inc.

DS39636D-page 159

PIC18F2X1X/4X1X

16.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the

clock line must match the proper Idle state. The clock

line can be observed by reading the SCK pin. The Idle

state is determined by the CKP bit (SSPCON1<4>).

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

16.3.7

SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI operation must be in Slave mode with SS pin

control enabled (SSPCON1<3:0> = 04h). When the SS

pin is low, transmission and reception are enabled and

the SDO pin is driven. When the SS pin goes high, the

SDO pin is no longer driven, even if in the middle of a

transmitted byte and becomes a floating output.

External pull-up/pull-down resistors may be desirable

depending on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI module

needs to operate as a receiver, the SDO pin can be

configured as an input. This disables transmissions

from the SDO. The SDI can always be left as an input

(SDI function) since it cannot create a bus conflict.

FIGURE 16-4:

SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI operation is in Slave mode

with

control

enabled

(SSPCON<3:0> = 0100), the SPI module

will reset if the SS pin is set to VDD.

2: If the SPI operation is used in Slave mode

with CKE set, then the SS pin control

must be enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO

bit 7

bit 6

bit 7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7

bit 0

Next Q4 Cycle

after Q2

↓

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式